The subject system and method are generally directed to the efficient generation of highly compact timing models for use in timing analysis of circuit designs. More specifically, the system and method include identification of a waveform invariant node for a given circuit path and optimized generation and configuration of a timing model based thereon.
With the increase in the size and complexity of circuit designs, divide-and-conquer methodologies executed using hierarchical design implementation and sign-off have become the preferred design approach. One of the extensively employed methodologies for hierarchical design implementation is based on the Extracted Timing Model (ETM). An ETM encapsulates the timing information of circuit paths of a given block, often although not necessarily in Synopsys Liberty Format (.lib format). The ETMs of different blocks of a design are extracted and plugged-in at the top-level for performing top-level timing analysis, with the extracted data abstracting or black-boxing certain details to reduce model space and analysis runtime. The ETM-based methodology is widely used both for design implementation and timing sign-off.
One quality of a circuit modeled in an ETM is the non-ideal transition (such as ramp-up or ramp-down of voltage) of signals as they traverse various components. Traditionally, this change has been assumed to be a linear rise or fall over a determined time period, and characterized accordingly by discrete input slew or output slew parameters. However, when modeling advanced technology nodes, this assumption has proven too inexact, and therefore actual sample points which more closely characterize input and output waveforms are computed to replace these parameters.
Each characterized waveform requires considerably more information than an equivalent slew, and therefore considerably more data storage space. If all slews in an ETM are replaced with waveform samples, the size of the ETM can increase dramatically (with a twenty-fold increase or more not uncommon). Additionally, determining each output slew involves simulating propagation of the corresponding input slew step-by-step through the circuit path, which is particularly runtime intensive when the slews are replaced with waveforms.
There is therefore a need for more efficient methodologies of representing a circuit path in a waveform-based ETM, and of generating said ETMs.